| 摘要 |
PURPOSE:To obtain a clock signal of non-overlap surely by using a clock signal having the largest delay as a gate input and adding an MOSFET whose drain is connected to a clock signal other than the gate input. CONSTITUTION:A biphase non-overlap clock signal is fed to a signal line 3 from drive circuits 1, 2. The signal delay time is increased more as the line 3 is remoter from the circuits 1, 2 because of a wiring resistance, a wiring capacitance and various load capacitances. When the drain of an MOSFET4 keeps a high level due to delay, even if the drain of an MOSFET5 is about to rise to a high level, since the FET4 is turned on, the drain of the MOSFET5 is kept forcibly to a low level. Even when the drain of the FET5 keeps a high level, similar suppressing operation is executed. Thus, the clock signal where non-overlap is guaranteed surely is obtained. |
