发明名称 Method and apparatus of reducing latch-up susceptibility in CMOS integrated circuits
摘要 Method and apparatus for controlling latch-up in a CMOS circuit senses a power supply transition, clamps the substrate to ground in response to sensing a power supply transition, and releases the clamp after the power supply transition. A charge pump pumps the substrate illustratively to -3 volts. The charge pump, clamping transistor and related elements are on the same CMOS substrate where latch-up is to be controlled. The substrate to ground capacitance of the substrate is increased to prevent localized substrate voltage disturbances which may induce latch-up.
申请公布号 US4571505(A) 申请公布日期 1986.02.18
申请号 US19830552249 申请日期 1983.11.16
申请人 INMOS CORPORATION 发明人 EATON, JR., SARGENT S.
分类号 H01L27/04;G05F3/20;G11C11/407;H01L21/822;H01L27/08;H01L27/092;H03K19/003;(IPC1-7):H03K17/693 主分类号 H01L27/04
代理机构 代理人
主权项
地址