| 摘要 |
PURPOSE:To open a bus immediately at congestion of processing of a slave module by acquiring a bus cycle in a synchronizing system and returning a reply to a command in data transfer and interruption to the bus. CONSTITUTION:When a request of data transfer takes place in a master module 30 at first, a bus request line ARB is set in a clock period succeeding thereto and a bus mater is acquired. The master module 30 adopts address bus processing flow at the succeeding clock period and transmits a bus ID, a command CMD and an address ADR. A command response CR is returned to the master module 30 at the next clock period from the slave module 32 receiving the address corresponding to the own logical address. In this case, if the execution is disabled, since, e.g., 01 is returned, the master module 30 gives up the said data transfer and opens the bus 10. |
