| 摘要 |
<p>PURPOSE:To shorten the response time of a word line to a non-selective mode by parallel-connecting a memory transistor farthest from a word line selection decoder to a voltage drop circuit in parallel and dropping linearly a potential given to each memory transistor at selection. CONSTITUTION:Transistors Tr3 and Tr4 are connected to a serially-connected voltage drop circuit 11 in parallel with a memory transistor B farthest from a decoder for making a word line in the selection state and non-selection state. After the transistor Tr3 is on, the Tr4 is on, and a gate potential of the transistor B drops. Then potentials of connection nodes of the Tr3 and Tr4 are lifted, a substrate electric field effect is applied, a threshold of the Tr3 is varied. Next, the gate potential of the transistor B is stabilized to the prescribed value lower than a gate potential of a transistor A nearest to the decoder. Then the potential given to each memory transistor at the word line selection drops in accordance with the distance, and the response time of the word line in a nonselective mode is shortened, whereby semiconductor integrated memory can be accessed quickly.</p> |
