Use of an electronic vernier for evaluation of alignment in semiconductor processing

摘要

An electronic vernier is presented which detects and quantifies misalignment between layers of material deposited upon a semiconducting wafer. Verniers may be constructed which evaluate alignment between two conducting layers, between two conducting layers and an insulating layer and between a semiconducting layer and a capacitive layer. Circuitry is described which shows how output from a vernier may be detected and quantified in order to evaluate the amount of misalignment.