发明名称 BUFFER MEMORY CONTROL SYSTEM
摘要 <p>PURPOSE:To utilize effectively a transmission line by applying deframing when meny pieces of generated information due to inter-frame codes exist and inserting a coding stop signal to the head of the frame subject to deframing to as to write the result to a buffer memory. CONSTITUTION:When switching control for switch circuits 2, 5 is executed in a four-frame period and meny coded data are generated, the coding stop signal S is outputted from a storage amount detection circuit 6 so as to apply slow speed shot. Since the coded data of the preceding frame is being transmitted for the period corresponding to the frame even with deframing the coded data is transmitted so as to utilize effectively the transmission line by slow speed shot. The period switching the circuits 2, 5 is not limited to the four-frame period but plural frame periods being >=2 frames are adopted and the capacity of buffer memories 3, 4 is decided depending on the period.</p>
申请公布号 JPS6118280(A) 申请公布日期 1986.01.27
申请号 JP19840137366 申请日期 1984.07.04
申请人 FUJITSU KK 发明人 NISHIZAWA YOSHIJI
分类号 H04B1/66;H04N19/50 主分类号 H04B1/66
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