| 摘要 |
PURPOSE:To perform DC component control and timing pilot signal component suppression control simultaneously through a simple circuit and even when a timing pilot component classified by systems becomes >=1/2 an identification level interval by improving a DC component and a timing pilot component suppression control system. CONSTITUTION:When an equalization state is excellent and the output signal 26 of an equalization state monitoring circuit is ''0'', a correction quantity input to an adder 21 is 0001, and 0001 or 1111 is added to the value in a register with an identification error signal 10. If the equalization state deteriorates, the signal 26 becomes ''1'', and 0100 or 1100 is added to the data in the register only when a maximum identification level is detected and the exclusive OR result of the signal 10 and a signal polarity signal 32 is ''0'', namely, when a signal outside the maximum identification level is detected. The delay of an equalization acquisition time is suppressed by increasing a correction quantity in case of equalization deterioration. A signal 25 is the detection signal of a maximum identification level detecting circuit 23 for an absolute value. |
