| 摘要 |
PURPOSE:To omit the cache directory update after block loading is terminated when the block loading is made to a cache memory, by loading a specific inspection bit onto the cache memory if readout data are not the one requested by a CPU. CONSTITUTION:When a command 101 and address signal 103 are sent from a CPU in response to the readout request of a word W3, the block of a prescribed column No. of the block group 6 of a cache directory 5 is read out by a middle- order address 105 from a register 1 and a hit signal 111 is outputted from a hit detecting circuit 10. Moreover, the block of a prescribed column No. of the block group 3 of a cache memory 2 is read out and the read out block is inputted in an error detecting circuit 8 together with an inspection bit C by means of the output of a main memory error detecting/inspection bit generating circuit 12. At a cache memory control circuit 13, a low-order address 106 is collated with an error detecting signal 109 and, when an error is confirmed, data read out to a data selecting circuit 14 from the block group 3 are abandoned. |
