| 摘要 |
PURPOSE:To improve the processing efficiency of an information processor without stopping the processing of the succeeding instruction by generating a false instruction in a processor A, and after executing the instruction, accessing a memory from a processor B. CONSTITUTION:A vector sum instruction VSM is executed in a vector instruction processing pipe-line 30. At the completion of the VSM, control signals such as a written-register specifying information REG and a writing request signal WRQ are sent to scalar instruction processing pipe-line 20 to write the calculated result in a general register GR/floating-point register FR21 in a scalar processor 2. Consequently, a false instruction generating circuit 263 is started and a false instruction for writing the calculated result in the register is formed. In addition, a selector 264 is controlled and the false instruction is stored in an operand fetching register 2c in stead of the scalar instruction. |
