发明名称 EXTRAPOLATION ARITHMETIC CIRCUIT FOR DIGITAL CONVERGENCE DEVICE
摘要 PURPOSE:To prevent the output of an abnormal correcting value by inhibiting an input of an arithmetic output to an adder when a subtractor is in borrow state, and bringing the output of the adder to a high level in overflow state. CONSTITUTION:When subtractors 9f, 9h are in borrow state, input inhibition circuits 9n, 9p are activated by the output of borrow detection circuits 9l, 9m and an output from the subtractors 9f, 9h is not inputted to adders 9g, 9i. When the adders 9g, 9i are in overflow state, the output of the overflow detection circuits 9q, 9r activates the high level output circuits 9s, 9t and the output of the adders 9g, 9i is brought all into high level. Thus, the output of the extrapolarion operating circuit is controlled so as to prevent an abnormal convergence correction current from flowing.
申请公布号 JPS6110386(A) 申请公布日期 1986.01.17
申请号 JP19840133675 申请日期 1984.06.26
申请人 MITSUBISHI DENKI KK 发明人 SUGIMOTO TAKAYUKI
分类号 H04N9/28;(IPC1-7):H04N9/28 主分类号 H04N9/28
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