| 摘要 |
This tetrad adder/subtracter exhibits as the main circuit a dual tetrad subtracter 1 and as the correction circuit a subtracting circuit 2 for subtracting the number 6 and does not exhibit a nines complement circuit for executing subtractive additions, but a fifteens complement circuit and, because of the use of a fifteens complement circuit, exhibits a second subtracting circuit 3 for subtracting the number 6, by means of which circuit 3, in the case of subtractive addition, the number 6 is subtracted from the fifteens complement number of the summand present at the A inputs. The subtractions are effected in a normal manner and the additions are effected by means of subtractive addition. In the case of subtraction, the complement bypassing is preactivated in the circuit 4; the subtracting circuit 3 is not preactivated. In the case of subtractive addition, the complementing is preactivated in the circuit 4 and the subtracting circuit 3 is preactivated. <IMAGE>
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