| 摘要 |
PURPOSE:To obtain a zero insertion circuit with simple circuit constitution by outputting a pulse signal from a serial input parallel shift register and utilizing the said pulse signal when the same high level of >=consecutive 5 bits is inputted. CONSTITUTION:A parallel data signal (a) is outputted as a serial data signal (c) from a parallel input serial output converting element 1, then same consecutive high level of >=5 bits is outputted as the signal (c), and when a control signal (h) enabling zero insertion is at a possible level, a pulse signal is outputted from an output data representing a level 5 clocks before among parallel data from the serial input parallel shift register 3. The shift operation of the converting element 1 is stopped by one clock's share by using the signal and the said signal is fed to a counter circuit 2 via an inverter 13 at the same time, the counting is stopped by one clock's share to retard a signal (d) as a load signal by a time inserted with zero. Further, an output signal of the inverter 13 is fed to a gate circuit 11 together with the signal (c) and zero is inserted to the signal (c) by bringing the output to a zero level. |
