| 摘要 |
<p>A two-state decoder circuit including a first-stage decoder circuit (7-1 to 8-2, 9, 10, 11), for decoding upper bits (A0 to A3) of an input signal, and a second-stage decoder circuit (4, 5, 6), which is activated by receiving a selected output signal of the first-stage decoder circuit and which decodes lower bits (A4 to A7) of the input signal. The first-stage decoder circuit is formed by a threshold-operation type logic circuit (11) which carries out selection or non-selection by comparing the input signal (9a, 10a) with a predetermined threshold level (VR), and the second-stage decoder circuit is formed by a diode-matrix circuit (D5 to D8). </p> |
