发明名称 |
DIGITAL PARALLEL CALCULATING CIRCUIT FOR POSITIVE AND NEGATIVE BINARY NUMBERS |
摘要 |
To increase the computing speed when forming the product of a first binary number (x) and a second binary number (y) and then adding (xy+z) a third binary number (z) by means of a multiplier (mw) and an adder (aw), the individual full-adder stages of the adder (aw) except the stage for the sign digit are inserted as an additional row between the next to the last row and the output row of the multiplier, the full-adder for the sign digit of the output row (az) being also omitted. The two omitted stages are replaced with a sign-correcting stage (vk). |
申请公布号 |
DE3267489(D1) |
申请公布日期 |
1986.01.02 |
申请号 |
DE19823267489 |
申请日期 |
1982.02.18 |
申请人 |
DEUTSCHE ITT INDUSTRIES GMBH;ITT INDUSTRIES INC. |
发明人 |
UHLENHOFF, ARNOLD |
分类号 |
G06F7/52;G06F7/00;G06F7/508;G06F7/53;G06F7/533;G06F7/544;G06F17/10;(IPC1-7):G06F7/544 |
主分类号 |
G06F7/52 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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