| 摘要 |
A complementary metal-oxide semiconductor master slice integrated circuit comprises a plurality of basic cells (41, 141; 42, 142; . . . ) in an internal functional gate region (22), each basic cell, which is a basic repetition unit, including a single P-channel metal-oxide semiconductor (41, 42, . . . ) and a single N-channel metal-oxide semiconductor (141, 142, . . . ) which are disposed linearly with respect to each other through an electrical isolation region. The plurality of basic cells are equidistantly disposed in parallel in a traverse direction of the internal functional gate region (22), without disposing any electrical isolation regions between the basic cells, so that the positions (101 DIFFERENCE 108, 91 DIFFERENCE 98) where longitudinal wirings are to be placed in a wiring zone (31, 32) correspond to the basic cells in a one-to-one manner. An electrical isolation between a plurality of logical gates structured in the internal functional region is achieved by applying a relatively positive voltage potential and a relatively negative potential to a P-channel metal-oxide semiconductor and an N-channel metal-oxide semiconductor included in the basic cells, respectively. Two metal-oxide semiconductors included in a basic cell are used as a complementary metal-oxide semiconductor by connecting them in a complementary manner, as necessary.
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