| 摘要 |
<p>An interface apparatus for coupling a multi-channel tester (11) to a high pin count logic circuit for use in testing the logic circuit is provided wherein a plurality of terminal electronics units (21) are coupled to each test channel of the multi-channel tester (11). Some of the terminal electronics (21) units are coupled to each other in parallel by at least one stimulus shift register (18), which serves to divide a serial stimulus vector among the terminal electronics units (21), and one response shift register (17), which serve to assemble the response data from several terminal electronics (21) units into a serial response vector. The serial stimulus vector is generated, and the serial response vector is analyzed by the multi-channel tester (11). The apparatus is capable of operating in one of a plurality of modes used for functional testing, parametric testing, and high speed scan path testing of the logic circuit.</p> |
