| 摘要 |
PURPOSE:To attain ease of establishment of a correct demodulation clock at a reception side with simple constitution by transmitting a signal which repeates inversion as low and high level at each 1 bit of a code synchronously with a transmission frame to an input signal. CONSTITUTION:A transmitter 10 activates a counter 13 by using a transmission clock from a clock generating circuit 12, the transmission clock is counted by one frame's share and a frame synchronizing signal generating circuit 14 generates a frame synchronizing signal. A signal l of an NRZ code synchronously with the transmission clock from a transmission data input terminal 11 is inputted respectively to an input of an EX-OR circuit 19 together with an output signal (k) of the least significant bit (LSB) of a counter 13 repeating alternately a low level and a high level at each bit of the code as the low level at an odd number bit and the high level at the even number bit. A signal of the NRZ code is converted into a split phase code, driven by an output circuit 17 and outputted from a transmission signal output terminal 18. |
