| 摘要 |
PURPOSE:To attain the operation check by each block of a device by combining a timing ROM and a ROM storing data for check so as to generate various check data signals. CONSTITUTION:An 8-bit output signal 2a is inputted to the timing ROMA3 as an address signal. Only one digit of each 8-bit signal is read as a series of single-bit signals (a), (b), (c)... respectively from the ROMA3. Said single bit is frequency-divided by counters B4, C5, D6... and the result is outputted respectively as address signals 4a, 5a, 6a.... The data signals 7a, 8a, 9a are read from data ROMs B7, C8, D9... recording respectively basic data for various checks and these signals are converted into the various check signals through parallel/serial converter 10 and buffers 11, 12....
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