发明名称 HIGH FREQUENCY SYNTHESIS CIRCUIT
摘要 PURPOSE:To suppress the reduction in an output at a fault to a value of nearly 3dB by constituting the titled circuit that a variable phase circuit inserted to one of two lines connecting two hybrids is controlled in response to the state of the final output. CONSTITUTION:Terminals of two 90 deg. hybrids 3, 4 are connected by the lines and the reflecting type variable phase circuit comprising a circulator 5 and lines 13, 14, 15 is inserted to one of the lines. A coupler 8 is to detect the final output state and when either of inputs 1a, 1b is interrupted for example, the coupling output is changed. The change is detected by a detector 9 and either of switches 11, 12 is driven by a controller 10 and the phase amount is controlled. As a result, the output is extracted only at an output terminal 2a. That is, even if one input is interrupted, the output reduction is suppressed to 3dB.
申请公布号 JPS60259001(A) 申请公布日期 1985.12.21
申请号 JP19840114554 申请日期 1984.06.06
申请人 HITACHI SEISAKUSHO KK 发明人 SEKINE KENJI;KANEKO YOUICHI;FUNAKI HARUHIKO
分类号 H01P5/04;H01P5/12;H01P5/16 主分类号 H01P5/04
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