| 摘要 |
PURPOSE:To arrange wirings, which apply reverse bias without crossing a VCC wiring and a grounding wiring, by aligning the arranging directions of a p- channel MOS transistor and an n-channel MOS transistor, to which gates are commonly connected, and arranging the transistors side by side in the direction perpendicular to the connecting direction of the gates. CONSTITUTION:A p type well region 2 is formed in a belt shape on the surface of an n type silicon substrate 1. Gate electrodes G1, G2, G3, G4 and the like are arranged in the direction perpendicular to the extending direction of said well region 2. Then CMOS transistors comprising pairs of the p-channel transistors and the n-channel transistors sharing the gate electrodes G1, G2, G3, G4 and the like, i.e., a pair of TRp1 and TRn1, a pair of TRp2 and TRn2, a pair of TRp3 and TRn3, a pair of TRp4 and TRn4 and the like are formed. Then reverse bias wirings +VBB and -VBB can be formed without crossing a VCC wiring and a GND wiring. |
