| 摘要 |
PURPOSE:To decrease the number of desired elements and to facilitate the pattern layout by using an input signal A as the power supply of a C-MOS inverter, applying an input signal B to the connection gates of a pair of MOS transistors (TR) constituting the C-MOS inverter and using the series connection points of said paired MOSTRS as an output terminal. CONSTITUTION:A p channel MOSTRQ21 is provided together with an n channel MOSTRQ22 and an n channel MOSTRQ23. The TRQ21 and TRQ22 constitute a C-MOS inverter, and the TRQ23 delivers an L level of the inverter. If B=H is satisfied with this C-MOS logical circuit, the TRs Q21 and Q22 are turned off and on respectively with an output C=L satisfied. Then the TRs Q21 and TR Q22 are turned on and off respectively with H=L. Then an output C=A is satisfied. In other words, the TRQ23 is turned off with the output C set at H when A=H is satisfied. While the TRQ23 is turned on with the C set at L when A=L is satisfied. That is, the signal A is separated by the signal B. In addition, just three using transistors suffice with the same structure as a C-MOS inverter. Thus the pattern layout is simplified.
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