发明名称 FALSE FAULT GENERATING SYSTEM
摘要 PURPOSE:To evaluate accurately and many times a fault processing function with generation of the same phenomenon by securing insertion of a false fault to an optional position via an optional phenomenon from the 2nd processor that usually executes a program. CONSTITUTION:A central processor 2 is connected to a main memory 1 and a magnetic disk controller 3, and a magnetic disk device 4 is connected to the controller 3. The processor 2 is connected to a service processor 5 via a phenomenon designating information register signal line 61 and a signal line 62 for register of error indicator flip-flop selecting information. The processor 5 contains a memory part 52 storing a false fault insertion program 521 and a processing part 51 which executes a false fault insertion instruction.
申请公布号 JPS60254248(A) 申请公布日期 1985.12.14
申请号 JP19840110631 申请日期 1984.05.30
申请人 NIPPON DENKI KK 发明人 NASU SADAO
分类号 G06F11/22;G06F11/267 主分类号 G06F11/22
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