| 摘要 |
PURPOSE:To improve the recording speed and to smooth gradation expression by adding a latch in addition to a latch receiving a parallel data of a shift register so as to take an accurate timing. CONSTITUTION:Latch circuits LA1, LA2 of >=2 stages are inserted between the shift register SR1 and an element driver. The 1st latch circuit LA1 receiving a parallel data from the shift register SR1 latches the parallel data and the latch circuit LA2 giving a data to the element driver of the most down-stream latches a latch output of the upperstream in the power application timing causing the desired density expression. Thus, an energizing control timing expressing a desired gradation is set.
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