发明名称 DYNAMIC RAM
摘要 PURPOSE:To reduce the peak current level which is supplied to a power supply line by dividing MOSFETs which precharges the data line of a memory array up to the power supply voltage level into plural groups and turning on these divided MOSFETs with time difference to make each data line perform a precharge action. CONSTITUTION:A 1-bit memory cell MC constituting a dynamic RAM consists of an information memory capacitor Cs and an address selecting MOSFET element Qm. The presence or absence of the charge of a capacitor Cs is detected according to the information on logic ''1'' or ''0''. When the information is read out, the element Qm is turned on and the Cs is connected to a common data line DL. Then the variation of the Cs is detected. Thus the size of the cell MC is reduced and the potential change of the line DL due to the charge amount stored in the Cs is converted into fine signals. These signals are detected by a sense amplifier SA connected to the lines DL and D'L' respectively. In this case, the amplifier SA consists of FET element Q1 and Q2 connected with cross to each other and can perform a differential operation.
申请公布号 JPS60246094(A) 申请公布日期 1985.12.05
申请号 JP19840100487 申请日期 1984.05.21
申请人 HITACHI SEISAKUSHO KK 发明人 KOBAYASHI MITSUTERU
分类号 G11C11/409;G11C11/34;(IPC1-7):G11C11/34 主分类号 G11C11/409
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