发明名称 |
Checking sequential logic circuits |
摘要 |
A sequential logic circuit includes means for checking, while the circuit is in operation, that it is stepping correctly from one state to the next. The current state of the circuit is encoded as X0-X3. That encoded value is compared with a predicted value Y0-Y3 derived in response to the previous state of the circuit itself and those signals that cause the transition from the previous to the current state. If the two do not match the circuit has not stepped to the correct state. Reduction in hardware is achieved by allowing certain states to share the same encoded value.
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申请公布号 |
US4556976(A) |
申请公布日期 |
1985.12.03 |
申请号 |
US19830517643 |
申请日期 |
1983.07.27 |
申请人 |
INTERNATIONAL COMPUTERS LIMITED |
发明人 |
HOWARTH, JAMES |
分类号 |
G06F11/08;G06F11/28;(IPC1-7):G06F11/00 |
主分类号 |
G06F11/08 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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