发明名称 POWER-ON RESETTING CIRCUIT
摘要 <p>PURPOSE:To increase the reset time with a miniature circuit by connecting a series circuit consisting of an n-MOS transistor (TR), a P-MOS TR and a capacitor between positive and negative power supplies and supplying a clock pulse to gate electrodes of both TRs. CONSTITUTION:A power-on resetting circuit is formed by connecting an n-MOS Tr4, a p-MOS Tr3 and a capacitor 5 is series between a positive power supply VDD and a negative power supply VSS. A clock signal 9 is supplied to the gate electrodes of both Trs 3 and 4 to obtain a reset signal output 8 from the junction 7 between the drain of the Tr3 and the capacitor 5 via an inverter 6. Thus it is possible to increase the time (reset time) during which the charging voltage of the capacitor 5 reaches the threshold value of the inverter 6. The reset time is also increased by increasing the cycle of the signal 9. In this way, the capacity of the capacitor 5 is reduced.</p>
申请公布号 JPS60241114(A) 申请公布日期 1985.11.30
申请号 JP19840098225 申请日期 1984.05.16
申请人 NIPPON DENKI KK 发明人 KANOU TOSHIYUKI
分类号 G06F1/24;G06F1/00 主分类号 G06F1/24
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