发明名称 LOGIC ANALYZER
摘要 PURPOSE:To make a sudden abnormal phenomenon apparent, and to analyze easily the abnormal phenomenon by adding variably the probe input impedance of a logic analyzer. CONSTITUTION:When detecting a factor for generating an abnormal phenomenon, a switch S is turned on, and set to a low impedance converting mode. As a result, it becomes a form which has connected in parallel a resistance and a capacity of a variable input impedance circuit 41 to an input resistance Rin and an input capacity C in of a comparator, and an input impedance of a logic probe 40 goes to low. When it is connected to a signal to be measured in this state, a load impedance seen from a circuit to be measured goes to low, and it attains a heavy load state to a usual logic circuit. As for a sudden phenomenon whose factor is a physical phenomenon (noise, etc.), the phenomenon appears more remarkably by the heavy load state, therefore, the abnormal phenomenon is made apparent, and the analysis can be advanced.
申请公布号 JPS60230243(A) 申请公布日期 1985.11.15
申请号 JP19840085217 申请日期 1984.04.27
申请人 YOKOKAWA HOKUSHIN DENKI KK 发明人 SAKURAI KAZUAKI
分类号 G01R31/28;G06F11/22 主分类号 G01R31/28
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