发明名称 STORAGE ELEMENT CIRCUIT
摘要 <p>PURPOSE:To always attain high speed operation and low power consumption operation without causing a difference in operating speed by providing a circuit setting a precharge voltage to an intermediate value at the high speed to cut off a DC path between two power supplies of a memory circuit. CONSTITUTION:When transistors (TRs) TR1, TR4 are turned on by a precharge signal, the level reaches a threshold value LLT2 of an inverter 5 higher than a threshold value VLT1 of an inverter 4 of a detection circuit 10 and until a TR3 is turned off, precharging is applied, and the common data line of a row selecting circuit 3 is precharged rapidly to an intermediate voltage. The precharge is started almost at the same time as the selection of column by the circuit 3 and finished before a row selection, the TRs TR2, TR4, TR10 shut off the DC path between the two power supplies of a memory element 2 of a memory matrix 1, and low power consumption requiring only the charging current to the parasitic capacitance of the circuit is obtained. Moreover, the initial state is ensured at all times by a discharge TR of the circuit 3 to attain high speed and low power consumption not causing no difference in the operating speed.</p>
申请公布号 JPS60224197(A) 申请公布日期 1985.11.08
申请号 JP19840079616 申请日期 1984.04.20
申请人 HITACHI SEISAKUSHO KK 发明人 SAWASE TERUMI;NAKAMURA HIDEO
分类号 G06F15/78;G11C16/06;G11C17/00;(IPC1-7):G11C17/00 主分类号 G06F15/78
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