发明名称 TIMING SIGNAL GENERATING CIRCUIT USING JOSEPHSON EFFECT
摘要 PURPOSE:To obtain a timing signal automatically at a desired time point by obtaining an OR between N pieces of signals and their complementary signals and then obtaining and outputting an AND of those signals. CONSTITUTION:The logical states of input signals A and -A are fixed when the signal A or -A is set at logic 1. Then a logical circuit 40 is switched. In the same way, it is decided by switching actions of logical circuits 41 and 42 that the logical states of input signals B and -B and input signals C and -C are fixed respectively. Then it can be decided that the logical states of signals A and -A as well as B and -B are fixed from a fact that a logical circuit 43 is switched to a voltage state.
申请公布号 JPS60223221(A) 申请公布日期 1985.11.07
申请号 JP19840078963 申请日期 1984.04.19
申请人 NIPPON DENKI KK 发明人 SONE JIYUNICHI
分类号 H01L39/22;H03K19/195 主分类号 H01L39/22
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