| 摘要 |
A high speed, low power bootstrap driver is disclosed for use in an MOS memory. The basic driver includes first and second enhancement mode transistors (12a, 14a) for receiving a digital input (16a). The drain of the first transistor (12a) is coupled to a high impedance depletion mode transistor (22a), and the drain of the latter transistor is coupled to the source of a low impedance transistor (26a). Another enhancement mode transistor (30a) is coupled via its sources to the drain of the second enhancement mode transistor (14a) and is coupled via its gate to the drain of the first enhancement mode transistor (12a). A capacitor (34a) is connected between the drain of the high impedance transistor (22a) and the drain of the second enhancement mode transistor (14a). When a low level input is received, the drain of the first enhancement mode transistor (12a) is rapidly bootstrapped to a high level voltage above the positive power supply for use as an output signal (18a). Delay means, such as an inverter (46, 48), are arranged to receive the input signal and apply a delayed input signal to the gates of said first and second enhancement mode transistors (12a, 14a). |
