| 摘要 |
PURPOSE:To obtain a memory access system of less time loss by dividing address information from a processor into two and converting one to a physical address by a memory management unit and sending the other to a memory as address information. CONSTITUTION:A logical address from a CPU1' is divided into two, and the upper address is inputted to a memory management unit (MMU) 2' through a bus 5'. The lower address is sent to a multiplexer (MPX) 3' directly through a bus 6' and is sent to a memory 4' by a row address selecting signal (RAS) from a timing generating circuit 8. Meanwhile, the upper address inputted to the MMU2' is already inputted to the MPX3' then after conversion to a physical address and is sent to the memory 4' when a column selecting signal (CAS) from the circuit 8 is outputted. Since the upper address is sent to the memory during address conversion in the MMU in this manner, the MMU and the row address input of the memory are operated in parallel. |
