发明名称 PACKET PROCESSING UNIT
摘要 PURPOSE:To improve processing capability by dividing a memory device used by a central processing unit for the processing, and a memory device for data storage for data communication, and providing another bus system for exclusive use of DMA. CONSTITUTION:A CPU1 has a control system bus 2, to which a ROM3, RAM4, line controller 5 receiving a data from a communication line, DMA controller in pairs with the line controller 5 and a data communication memory device 7 exclusively used for the storage of transmission/reception data are connected. Moreover, all the line controllers and the data communication memory devices 7 are connected respectively via the DMA connection line provided in pairs to the control system bus connection line. Furthermore, an access request circuit 9 to be accessed by the CPU1 to a device connected to the DMA system bus 8 is connected to the control system bus 2.
申请公布号 JPS60219849(A) 申请公布日期 1985.11.02
申请号 JP19840076802 申请日期 1984.04.17
申请人 NIPPON DENKI KK 发明人 SENTOUDA JITSUO
分类号 G06F13/28;H04L12/70 主分类号 G06F13/28
代理机构 代理人
主权项
地址