| 摘要 |
PURPOSE:To reduce the number of gate stages by providing a basic logical gate respectively between the 2nd flip-flop and the 3rd flip-flop and between the 2nd, 3rd flip-flops and the 1st flip-flop. CONSTITUTION:A non-inverting output Q11 of a data flip-flop (hereinafter DFF) 11 is given to a data input D12 of a DFF12 and an output of an NOR gate 51 is given to a data input D11. A noninverting output Q13 of a DFF13 is given to another input of an NOR gate 51. An inverting output Q12 of the DFF12 is given to an input and an output 02 of an NOR gate 52 and a mode switching signal M is inputted to another input of the NOR gate 52. An output of the NOR gate 52 is given to a data input D13 of the DFF13 and a clock is applied to clock inputs C11-C13 of the DFF11-DFF13. |
