| 摘要 |
PURPOSE:To enable to perform a high-speed operation by a method wherein the lead-out electrode of a field-effect transistor is composed of a polycrystalline silicon layer and a metal silicide layer, thereby enabling to contain a high-speed J-FET. CONSTITUTION:In the case of a semiconductor integrated circuit containing a bipolar transistor and a J-FET composed of a drain 20, a source 21, a back-gate contact 24, a channel 25, a top gate 26, an electrode and the like, a lead-out electrode is composed of a polycrystalline silicon layer 27 formed adjoining to a top gate 25 and a metal silicide layer 28 formed on the polycrystalline silicon 27. When the lead-out electrode is formed as above-mentioned, a gate electrode can be provided at a suitable position utilizing a low resistance lead-out part, and as a result, the gate length L can be made shorter. Besides, the gate impedance can also be made smaller, thereby enabling to obtain a high-speed J-FET. |
