发明名称 VOLTAGE COMPARATION CIRCUIT
摘要 PURPOSE:To shorten a time required for the clear of a capacitor by connecting a level limiter circuit to the drain output of a differential MOSFET to reduce an output voltage difference. CONSTITUTION:When the level difference between a reference voltage Vref and an input signal (in), a drain voltage is sharply changed in accordance with gain due to the amplifying operation of differential MOSFETs Q1, Q2. If the drain voltage is changed so as to exceed the threshold voltage of MOSFETs Q9, Q10 by regarding a level limiter voltages as a reference, the MOSFETs Q9, Q10 is turned to the ON state, so that a load resistance value is suddenly reduced. Consequently, amplification gain is limited, so that the drain voltage of the differential MOSFET Q1 or Q2 is practically limited to a fixed level.
申请公布号 JPS60213118(A) 申请公布日期 1985.10.25
申请号 JP19840067698 申请日期 1984.04.06
申请人 HITACHI SEISAKUSHO KK 发明人 NAGAYAMA YOSHIHARU
分类号 H03K5/08;H03K5/24 主分类号 H03K5/08
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