| 摘要 |
PURPOSE:To prevent the generation of a latch-up by completely separating grounding lines for a bipolar element and an MOS element and connecting the grounding line for the bipolar element to an isolating layer. CONSTITUTION:A P type silicon substrate 1 as an emitter in a parasitic P-N-P transistor 21 has the same potential as a grounding line 18 for a bipolar element through an isolating layer 4. The P type silicon substrate 1 as an emitter in a parasitic P-N-P transistor 23 has the same potential as the grounding line 18 for the bipolar element through the isolating layer 4 while potential on the plus side of a power supply is applied to an N type silicon epitaxial layer 3 as a base through a power supply line 20 and an N<+> diffusion layer 15. That is, the parasitic P-N-P transistor 23 is brought to a reverse bias state-for example, the transistor 23 is not turned ON even when the potential of the grounding line for the bipolar transistor varies more or less, thus eliminating a latch-up. |
