| 摘要 |
PURPOSE:To increase the gate reverse withstand voltage of a GTO by a method wherein, in split formation of a base layer and an emitter layer in the same plane of a wafer, the base layer is selectively epitaxially grown according to the pattern of the emitter layer, where the emitter layer is provided. CONSTITUTION:P1, N1, and P2 layers are formed by using an Si wafer, and SiO2 layers are generated by selectively oxidizing the exposed surface, and a window based on a split cathode pattern is opened on the P2 layer by etching. Next, a P2<-> layer is epitaxially grown on the exposed surface of the P2 layer by utilizing that crystals do not grow on the SiO2 film, and an N2 layer is formed in the P2<-> layer by diffusion. Thereafter, the SiO2 film is removed, and a cathode electrode K, a split gate electrode G, and an anode electrode A are formed on the N2 layer, P2 layer, and back of the P1 layer, respectively. Thus, the variation in surface concentration of the P2<-> base layer is eliminated, where the N2 emitter layer is provided, resulting in the improvement in gate reverse withstand voltage. |
