| 摘要 |
PURPOSE:To contrive the increase in integration by a method wherein the first active layer and an interlayer insulation on a single crystal Si substrate are provided with the second active layer produced by the melting growth of poly Si, and the single crystal region of each active layer is made as a basic logical cell region, and the element isolating region as the wiring channel. CONSTITUTION:The first active layer made of N-MOSFET on the Si substrate is vertically connected to the second active layer of P-MOSFET with the through- holes 41-44 of the interlayer insulation layer, and the numeral 40 is made as the power source wiring, 45 ground wiring, 46 P-MOSFET, and 47 element isolating region, thus constituting a basic cell of 2-input OR gate. This construction necessitates only the power source or only the ground wiring 40 or 45 in each of the upper and lower layers constituting the basic cell, and enables the reduction in cell width by unnecessary wirings. Four equivalent terminals A, B, and Y are given to a streak of input or output signal: the more the number of equivalent terminals, the more increases the degree of freedom in connection with the same signal among basic cells; besides, the intersections of wiring reduce, and the wiring channel region can be reduced by the decrease in the number of through holes. |
