| 摘要 |
PURPOSE:To execute a processing without disturbing an advance control by bypassing the result of an address calculation and delivering it to the succeeding instruction, when it is detected that the result of an address generating instruction is requested by its succeeding instruction. CONSTITUTION:Register number comparing circuits 20, 21, 30 and 31 are connected to instruction registers 10-14, also the instruction of the register 10 is decoded by an instruction decoder 1, its result is set to each index and base register 70, 71, and its contents and a displacement D of the register 10 are added by a three-input adder 72 and set to a register DAR73. In such a state, it is detected by a comparator 21 or 20 that a store register of an instruction of a load address system is the same as the base or index register of the next instruction, the output line 73l of the DAR73 is selected by a selector 61 or 60, and set to the register 71 or 70.
|
