| 摘要 |
PURPOSE:To access to a low speed input/output device without lowering a speed of operation of central processing unit by accessing once to the input/output device that operates at low speed while the central processing unit executes access instruction of two bytes over two clock periods. CONSTITUTION:During the course in which a microprocessor MPU executes access instruction of two bytes, address a1 sent out in the first clock period t1 and effective data d1 sent out in the second clock period are transmitted to a circuit controlling section IO, and written by an input/output device selection signal cs transmitted to the circuit controlling section IO in the second clock period t2 and an input/output write/read signal cvw. Accordingly, the circuit controlling section IO operates at low speed of 1/2 of clock signals phi1 and phi2 that operate the operation speed of the microprocessor MPU to the same as the circuit controlling section IO in level. |
