| 摘要 |
PURPOSE:To enable to attain high integration at a master slice approach integrated circuit by a method wherein a reference level is supplied from a reference level generating circuit to basic cells of eight pieces, and moreover resistors in the respective basic cells are extended in parallel with the reference level generating circuit. CONSTITUTION:A reference level generating circuit is put in the direction to cross at right angles with an electric power source wiring VCC at the center of a rectangular block surrounded by electric power source wirings VEE, basic cells BC of respective four pieces are put on blocks on one side and on another side divided into two pieces according to the reference level generating circuit thereof to form the 1 block 8BC construction. The reference level generating circuit supplies a reference level to the cells BC of eight pieces thereof. Moreover resistors in the cells BC are put in order in parallel with the reference level generating circuit, namely in parallel with the line VCC. By forming a layout as mentioned above, high integration can be attained, and moreover a change to the two electric power source system from the one electric power source system is facilitated, and moroover the wirings are facilitated. |
