发明名称 PROCESSING SYSTEM FOR PROCESSOR FAULT
摘要 PURPOSE:To attain the quick recovery or relief for a processor fault by executing forcibly a fault processing program by a CPU when the CPU gives an access to an unpacked space of a memory. CONSTITUTION:A time circuit 3 is provided in addition to a fault processing program data transmission circuit 4, and a CPU1 gives accesses to main memories 2-1 and 2-2. Then the programs are sent successively and forcibly to the CPU1 from the circuit 4 to relieve the fault processing for execution of the prescribed processing in case it is detected from collation with the prescribed time of the circuit 3 that no transfer end signal is sent to the CPU1 from memories 2-1 and 2-2 even after a prescribed period of time elapses.
申请公布号 JPS60193055(A) 申请公布日期 1985.10.01
申请号 JP19840049761 申请日期 1984.03.15
申请人 FUJITSU KK 发明人 HAYASHI HIDENORI
分类号 G06F11/00;G06F11/07 主分类号 G06F11/00
代理机构 代理人
主权项
地址