| 摘要 |
PURPOSE:To improve the reliability of the read-out data by correcting an error covering two bits after generating a correction signal which shows the order of bits having errors in the reproduction data bit groups according to each sum among vectors of each column of a check matrix. CONSTITUTION:The numbers of rows and columns of a check matrix H are decided in response to the numbers of check bits and data bits respectively. At the same time, different patterns are given to column vectors R0-R7 respectively of the matrix H. The bit number showing ''1'' is defined as an odd number in each pattern. A BAG buffer gate produces a correction signal CR which shows the order of bits having errors in the reproduction data bit groups shown according to each sum among vectors R0-R7 and in response to a syndrome S, i.e., a decision bit group obtained by giving an adverse replacement to a decision matrix (S)T. The signal CR is given to a correction circuit CRC. Thus the circuit CRC corrects an error covering two bits of the reproduction bit group by means of the signal CR. |
