| 摘要 |
PURPOSE:To attain stable operation over a broad band even at a high frequency region and to decrease power consumption by adopting the PLL circuit constitution provided with an analog frequency divider added with a feedback circuit and a means for varying a bias voltage of the frequency divider by an output of a loop filter. CONSTITUTION:The anlog frequency divider 20 utilizes the parametric operation due to the nonlinearity of a capacitor between terminals of a diode D31 and the mixer operation to continue it and is operated with low consumption even at a high frequency region. Since the frequency divider 20 takes charge of the high speed operation, a prescaler 21 saves a frequency divider operated in a high speed and having large power consumption. When the bias voltage to the frequency divider 20 is changed in response to an input frequency as the bias voltage is decreased with the higher input frequency, the frequency dividing band is widened. Then the frequency synthesizer with a broad band and less power consumption is realized by providing a voltage controller 22 changing the bias voltage of the frequency divider 20 in response to the output voltage of a filter 12. In this case, the output of the voltage controller 22 is connected to a terminal 33 of the frequency divider 20a and the bias voltage of the frequency divider is changed as stated above. |
