| 摘要 |
PURPOSE:To obtain a PLL circuit which causes no out-of-synchronism by varying continuously a time constant of an LPF in accordance with an output signal of an integration circuit, and varying continuously a capture range of the PLL circuit. CONSTITUTION:When an AM stereo IF signal applied to an input terminal 10 reaches an amplitude limit level L1 at a time t1, an output signal of an integration circuit 17 rises in accordance with an integral constant, and reaches a prescribed level L2 at a time t2. The signal varied in this way is amplified by a DC amplifier 18, and thereafter, applied as a control signal to an LPF12, and a time constant of the LPF12 becomes larger gradually in accordance with the control signal. When an output signal level of the circuit 17 becomes L2, the level of the control signal becomes a prescribed value, the time constant of the LPF12 becomes a prescribed value, and a variation of the time constant stops. Therefore, a capture range of a PLL circuit starts a decrease at the time t1, and becomes narrow at the time t2. In that case, a variation of the control signal is slower than the capture response speed of the PLL circuit, therefore, even if the capture range is varied, no out-of-synchronism is generated. |
