| 摘要 |
PURPOSE:To attain both two-byte transfer and one-byte data transfer even when memory is extended by providing a bus switching device which accesses the memory, word by word, and, byte by byte, selectively at any time. CONSTITUTION:When one word (two bytes) is transferred from an eight-bit input/output port 7 to the memory 5, an upper data strobe signal becomes active on the start of the DMA transfer cycle of direct memory access (DMA) 2. Consequently, memory 51 is accessed and further a high-order byte indication signal is also active, the bus switching device 4 operates to connect buses 23 and 24, and 21. Then, data from the port 7 is stored in the high-order byte side memory 51 through a signal line 30. Data of next two bytes is transferred in the same sequence to low-order side byte memory 52 and stored in the low-order byte side memory 52 through a signal line 31 at this time, so the bus switching device 4 does not operate. Extended memory 6 is exactly the same. |
