| 摘要 |
PURPOSE:To allow a main CPU to monitor the interruption processing operation of a slave CPU and to perform fine control over the slave CPU by providing an interruption signal generating circuit and an interruption signal resetting circuit. CONSTITUTION:The main CPU1 inputs an interruption request signal 21 to an inverted NMI signal generating FF51, which is then reset. Then, the FF51 inputs an inverted NMI signal 24 to the slave CPU2. The interruption is accepted unless the CPU2 is in a stop state, and a signal MI25 for the timing of instruction fetch is inputted to the inverted NMI signal resetting circuit 61. Then, the circuit 61 inputs an NMISFF set signal 22 to the FF51, which is set. Then, the setting state is reported to the CPU1 with a slave CPU interruption monitor signal 23 and the CPU1 is allowed to monitor the interruption state of the CPU2 and perform fine control over the CPU2. |
