发明名称 COUNTER CIRCUIT
摘要 PURPOSE:To prevent the occurrence of a through current by using a bootstrap circuit, which has a MOS capacity as the variable capacity, as a load circuit of a latch circuit. CONSTITUTION:An address counter which outputs individual bits or the like of a refresh address consists of the load circuit or the like of the bootstrap circuit which has FFMOS capacities C1 and C2 of cross-connected MOSFETs Q1 and Q2 as variable capacities and consists of MOSFETs Q9-Q11, Q6, Q7, etc. When a high-level clock phi is inverted to the low level and a low-level inverted clock anti-phi is inverted to the high level in the initial state, the capacity C1 forms a capacity by the high level of a node N3 and is precharged, and the gate of an FETQ9 is boosted to a power source voltage, but the capacity C2 does not form a capacity, and the FETQ9 is turned off though the clock anti-phi is in the high level, and this through current is not flowed through the turned-on driving MOS FETQ2. The level of the bootstrap output is compensated by a dynamic pull-up circuit, and an unnecessary through current is prevented to reduce the power consumption of a refresh address counter or the like.
申请公布号 JPS60187995(A) 申请公布日期 1985.09.25
申请号 JP19840042031 申请日期 1984.03.07
申请人 HITACHI SEISAKUSHO KK 发明人 SATOU KATSUYUKI
分类号 G11C11/406;G11C11/34;(IPC1-7):G11C11/34 主分类号 G11C11/406
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