发明名称 MANUFACTURE OF BURIED METAL GATE VERTICAL FIELD EFFECT TRANSISTOR
摘要 PURPOSE:To obtain a preferable pattern without irregular surface without burr at the pattern edge and to obtain a boundary having no oxide nor damage on a GaAs layer by forming a mask layer having a lower layer of narrow sectional structure than an upper layer to form a buried metal layer. CONSTITUTION:A resist pattern 15 is formed on the upper surface of a wafer 30, and a GaAs layer 14 is selectively etched. Then, after a resist film 15 is dissolved and removed with acetone, with the film 14 as a mask an AlGaAs layer 13 is etched. In other words, an etchant which does not operated on the layer 14, but operates only on the layer 13 such as HF etchant is used to etch the layer 13. In this case, the edge of the layer 13 of lower side is slightly intruded into the inside from the layer 4 of the upper side, and sidewisely etched. Thus, the layer 13 which is narrower in section than the layer 14 to form the upper layer is a lower layer in a mask layer 31 of a 2-layer structure. Then, the layer 31 is used to form a buried metal layer of high melting point metal to become the gate electrode is formed by a lift-off method.
申请公布号 JPS60186070(A) 申请公布日期 1985.09.21
申请号 JP19840040397 申请日期 1984.03.05
申请人 NIPPON DENSHIN DENWA KOSHA 发明人 ANDOU SEIGO;ASAI HIROMITSU;OE KUNISHIGE
分类号 H01L21/306;H01L29/417;H01L29/80 主分类号 H01L21/306
代理机构 代理人
主权项
地址