| 摘要 |
PURPOSE:To apply real-time processing using a memory number possible for realization by providing plural stages of converting circuits converting a signal inputted to an input terminal into other signal represented in less bit number than that of the input signal just before the discriminator. CONSTITUTION:An address bit part of a packet represented on a network is extracted by an address detector via a receiver and inputted to a bit pattern discriminator. The high-order 4 bits of the inputted 6-bit address are inputted to the 1st ROM3-1. Then the output is inputted to the 2nd ROM3-2 together with the 5-th bit of the input address. Then the said output is inputted to the 3rd ROM3-3 together with the 6 bits of the input address via a latch 3-5. Logical 1 or 0 is outputted according to the address to be selected and whether or not the packet is fetched is decided. |
